1. Technical Field
This disclosure generally relates to electronic design automation. More specifically, this disclosure relates to methods and apparatuses for legalizing a portion of a circuit layout.
2. Related Art
Advancements in process technology have impacted IC manufacturing in two key ways. First, scaling of device geometry achieved through sub-wavelength lithography has facilitated packing more devices in a chip. Second, different process recipes have enabled manufacturing of heterogeneous devices with different threshold and supply voltages in the same die. The result of these improvements, however, has been an explosion in the number of design rules that need to be obeyed in the layout. Instead of simple width and spacing rules, today's technologies prescribe complex contextual rules that have to be obeyed for manufacturability.
The increase in the number of rules has complicated the task of creating design rule clean layouts, i.e., layouts that do not have design rule violations. Creating design rule clean layouts for digital circuit designs may be possible if standard cell layouts are available as building blocks, and placement and routing tools are extended to address the design rules.
Unfortunately, this approach does not work for analog, RF and custom circuit designs. This is because such layouts are typically created manually using layout editors. Therefore, correcting design rule violations requires tedious manual edits. Furthermore, analog and RF circuit designs undergo multiple iterations between the circuit sizing and layout creation. This further complicates the issue of creating design rule clean layouts.